This disclosure concerns circuits and methods configured to adjust the voltage applied to control a bit cell transistor that switches a read bias current through addressed magnetoresistive memory bit cell elements in a memory array, during memory read operations.
In memory arrays, bit cells can be addressed separately according to their word line addresses, and when addressed are coupled to bit positions of memory words that are input (written) or output (read). The bit cells at a given bit position, for all the word lines, occupy successive locations along the associated bit line and source line of that bit position. When the word line of a bit cell is addressed, the addressed bit cell conducts current from a biasing source, at an amplitude according to the operational and logic states of the bit cell. That current passes through a portion of the bit line to bit cell, and then from the bit cell through a portion of the source line, when conducting from the biasing current source to current sink.
Because the bit cells have different locations along the bit line and the source line, namely nearer to the far end of one or the other of the bit line and source line, the relative lengths of the bit line and source line conductors coupled in series with the bit cell differ, according to the location of the bit cell in the array. Differences in length lead to differences in the distribution of resistance in series with the bit cell, between the bit line and source line side, even if the total resistance is the same because when the bit line is relatively shorter, the source line is correspondingly longer, and vice versa.
It is advantageous to accommodate certain effects caused by differences in the distribution of resistances, particularly in magnetoresistive bit cell memories.